DRAM, FLASH, and SRAM are the three major conventional semiconductor memories on the market. The manufacturing cost of DRAM is the lowest. However, in addition to shortcomings such as the need for refreshment, relatively low speed and high power consumption, DRAM is volatile. Consequently, a DRAM loses data when the power is turned off. FLASH memory is non-volatility, but is very slow. The write cycle endurance for a FLASH memory is less than one million cycles. This write cycle endurance limits the application of FLASH memories in some high data rate market. SRAM is a fast memory. However, SRAM is volatile and takes too much silicon area per cell. In search of a universal random access memory that offers high speed, non-volatility, small cell area, and good endurance, many companies are developing thin film Magnetic Random Access Memories (MRAM).
Conventional MRAMs can be fabricated with a memory cells using a variety of magnetic elements, such as an Anisotropic Magnetoresistance (AMR) element, a Giant Magnetoresistance (GMR) element, and a Magnetic Tunneling Junction (MTJ) stack. For example, a conventional MTJ stack is relatively simple to manufacture and use. Consequently, an MRAM is used as the primary example herein.
The magnetic field for changing the orientation of the changeable magnetic vector is usually supplied by two conductive lines that are substantially orthogonal to each other. When electrical current passes through the two conductive lines at the same time, two magnetic fields associated with the current in the two conductive lines act on the changeable magnetic vector to orient its direction.
FIG. 1A depicts a portion of a conventional MRAM 1. The conventional MRAM includes conventional orthogonal conductive lines 10 and 12, conventional magnetic storage cell having a conventional MTJ stack 30 and a conventional transistor 13. In some designs, the conventional transistor 13 is replaced by a diode, or completely omitted, with the conventional MTJ cell 30 in direct contact with the conventional word line 10. The conventional MRAM 1 utilizes a conventional magnetic tunneling junction (MTJ) stack 30 as a memory cell. Use of a conventional MTJ stack 30 makes it possible to design an MRAM cell with high integration density, high speed, low read power, and soft error rate (SER) immunity. The conductive lines 10 and 12 are used for writing data into the magnetic storage device 30. The MTJ stack 30 is located on the intersection of and between conventional conductive lines 10 and 12. Conventional conductive line 10 and line 12 are referred to as the conventional word line 10 and the conventional bit line 12, respectively. The names, however, are interchangeable. Other names, such as row line, column line, digit line, and data line, may also be used.
The conventional MTJ 30 stack primarily includes the free layer 38 with a changeable magnetic vector (not explicitly shown), the pinned layer 34 with a fixed magnetic vector (not explicitly shown), and an insulator 36 in between the two magnetic layers 34 and 38. The insulator 36 typically has a thickness that is low enough to allow tunneling of charge carriers between the magnetic layers 34 and 38. Thus, the insulator 36 typically acts as a tunneling barrier between the magnetic layers 34 and 38. Layer 32 is usually a composite of seed layers and an antiferromagnetic (AFM) layer that is strongly coupled to the pinned magnetic layer. The AFM layer included in the layers 32 is usually Mn alloy, such as IrMn, NiMn, PdMn, PtMn, CrPtMn, and so on. The AFM layer is typically strongly exchanged coupled to the pinned layer 34 to ensure that the magnetic vector of the pinned layer 34 is strongly pinned in a particular direction.
When the magnetic vector of the free layer 38 is aligned with that of the pinned layer 34, the MTJ stack 30 is in a low resistance state. When the magnetic vector of the free layer 38 is antiparallel to that of the pinned layer 34, the MTJ stack 30 is in a high resistance state. Thus, the resistance of the MTJ stack 30 measured across the insulating layer 34 is lower when the magnetic vectors of the layers 34 and 38 are parallel than when the magnetic vectors of the layers 34 and 38 are in opposite directions.
Data is stored in the conventional MTJ stack 30 by applying a magnetic field to the conventional MTJ stack 30. The applied magnetic field has a direction chosen to move the changeable magnetic vector of the free layer 30 to a selected orientation. During writing, the electrical current I1 flowing in the conventional bit line 12 and I2 flowing in the conventional word line 10 yield two magnetic fields on the free layer 38. In response to the magnetic fields generated by the currents I1 and I2, the magnetic vector in free layer 38 is oriented in a particular, stable direction. This direction depends on the direction and amplitude of I1 and I2 and the properties and shape of the free layer 38. Generally, writing a zero (0) requires the direction of either I1 or I2 to be different than when writing a one (1). Typically, the aligned orientation can be designated a logic 1 or 0, while the misaligned orientation is the opposite, i.e., a logic 0 or 1, respectively.
FIG. 1B depicts a conventional method 50 for fabricating the conventional MRAM 1. The isolation transistor 13 is formed on a silicon wafer (not shown), via step 52. The conventional word line 10 is then fabricated using conventional metal layer processes, via step 54. The conventional MTJ stack 30 is then provided, via step 56. Step 56 includes a physical vapor deposition (PVD) process to deposit the multilayer structure and patterning the multilayer structure into the conventional MTJ stack 30 using photolithography and etching processes. After the dimensions of the conventional MTJ 30 are defined in step 56, a layer of dielectric is typically deposited around and on the top of the conventional MTJ stack 30, via step 58.
FIG. 1C depicts the conventional MTJ stack 30 after deposition of the conventional dielectric layer 40 in step 58. The conventional dielectric layer 40 insulates the conventional MTJ stack 30, preventing the conventional MTJ stack 30 from shorting to other elements of the conventional MRAM 1. The conventional dielectric layer 40 may also be used for readying the wafer (not shown) for processes following formation of the conventional MTJ stack 30, such as metal line fabrication. The dielectric commonly used for the conventional dielectric layer 40 in the CMOS industry is SiO2, which can be deposited and etched conveniently with the widely used CMSO processes. It is also a common practice to deposit the dielectric layer on the full wafer so both the edges and the top of the conventional MTJ slack 30 are covered and protected.
Referring to FIGS. 1B and 1C, if the top of the conventional MTJ stack 30 is covered by the conventional dielectric layer 30, a photolithography step and an etching process are used to open a via (not shown) to the top of the conventional MTJ stack 30, via step 60. Thus, the bit line 12 can make contact with the conventional MTJ stack 30. The bit line 12 is then fabricated with conventional CMOS processes, via step 62. Finally, any back-end processing required to complete formation of the conventional MRAM 1 are performed, via step 64.
Although the conventional method 50 functions, one of ordinary skill in the art will readily recognize that the performance of the conventional MRAM 1 may degrade due to processing occurring after formation of the conventional MTJ stack 30. The processing temperature in step 62 or the conventional bit line 12, as well as other following on processes in step 64, can be a few hundred degrees Celsius. At such a temperature, the oxygen in the conventional dielectric layer 40 surrounding the conventional MTJ stack 30 can diffuse into the conventional MTJ stack 30. This oxygen can oxidize the magnetic materials used in the conventional free layer 38 and the conventional pinned layer 34. The magnetic properties of the conventional magnetic layers 34 and 38, such as the effective thicknesses and the coercivities, change depending on the degree of oxidation. Consequently, the conventional magnetic layers 34 and 38 may not behave as expected or desired. Furthermore, the oxygen can diffuse along the insulator 36 that acts as a tunneling barrier between the pinned layer 34 and the free layer 38. The oxygen can further oxidize the interfaces between the insulator 36 and the magnetic layers 34 and 38. As a result, the resistance of the conventional MTJ stack 30 increases and the variation in resistance with the direction of the magnetic vector of the free layer decreases (the Magnetoresistance), causing a deterioration of signal of the MRAM device. Thus, performance of the conventional MTJ stack 30 may be compromised.
Accordingly, what is needed is a method and system for providing a magnetic memory capable of having improved reliability and performance between elements.